Dynamic random access memory (DRAM) may have more than one internal memory bank. The DRAM is normally refreshed responsive to a refresh command that is periodically issued to the DRAM by a memory controller. When the DRAM receives a refresh command, the internal memory banks wait for a time period to complete a ReFresh Cycle (tRFC) before any of the internal memory banks can be accessed by a read or a write operation. As the capacity of DRAM increases, the tRFC may also increase. For example a 1 Gigabyte (Gb), a 2 Gb, a 4 Gb, and a 8 Gb double data rate (DDR) 3 DRAM may have a tRFC of 110 nanoseconds (ns), 160 ns, 300 ns, and 350 ns, respectively.
In a memory subsystem that supports multiple memory ranks, refresh commands between any two memory ranks are typically not overlapped. Overlapping the refresh commands increases the probability that an incoming read command will wait (for the overlapping refresh cycles to complete) before the read command can be sent to the DRAMs. To avoid overlapping refresh commands, an interval timer may be used to equally space refresh commands issued by the memory controller. Under some circumstances (e.g., during link retraining), the memory controller may place the DRAM in a self-refresh mode. During the self-refresh mode, the DRAM may not wait for refresh commands from the memory controller to initiate a refresh. The DDR DRAM specification states that a memory controller issue at least one refresh command after the DRAM exits from a first self-refresh mode and before the DRAM enters into a second self-refresh mode.
When a memory controller determines that a number of transmission errors occurring at a high-speed memory bus exceeds a predetermined threshold, the memory controller may initiate a link retraining process to resynchronize the high-speed memory bus to reduce the transmission errors. As part of the link retraining process, the DRAM may be placed in a self-refresh mode. After the link retraining process has completed, the DRAM may come out of the self-refresh mode. If the memory controller determines that the number of transmission errors occurring at the high-speed memory bus again exceeds the predetermined threshold, the memory controller cannot initiate a second link retraining. Initiating a second retraining would cause the DRAM to be placed into a second self-refresh mode. However, placing the DRAM in a second self-refresh mode may violate the DDR DRAM specification, because the memory controller may not have issued at least one refresh command to the DRAM after the DRAM exited from the self-refresh mode and before the DRAM entered into the second self-refresh mode.